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AT86RF231
Note that AWAKE_END interrupt can usually not be seen when the transceiver enters
TRX_OFF state after RESET, because register 0x0E (IRQ_MASK) is reset to mask all inter-
rupts. In this case, state TRX_OFF is normally entered before the microcontroller could modify
the register.
The interrupt handling in Extended Operating Mode is described in Section 7.2.5 “Interrupt Han-
dling” on page 67 .
If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be
read from IRQ_STATUS register even if the interrupt itself is masked. However, in that case no
timing information for this interrupt is provided.
The IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04,
TRX_CTRL_1). The default behavior is active high, which means that pin IRQ = H issues an
interrupt request.
If "Frame Buffer Empty Indicator" is enabled during Frame Buffer read access the IRQ pin has
an alternative functionality, refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152 for
details.
6.6.2
Register Description
Register 0x0E (IRQ_MASK):
The IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is enabled
if the corresponding bit is set to 1. All interrupts are disabled after power up sequence (P_ON
state) or reset (RESET state).
Bit
7
6
5
4
3
2
1
0
+0x0E
Read/Write
Reset Value
MASK_BAT_LOW
R/W
0
MASK_TRX_UR
R/W
0
MASK_AMI
R/W
0
MASK_CCA_ED_DONE
R/W
0
MASK_TRX_END
R/W
0
MASK _RX_START
R/W
0
MASK _PLL_UNLOCK
R/W
0
MASK _PLL_LOCK
R/W
0
IRQ_MASK
If an interrupt is enabled it is recommended to read the interrupt status register 0x0F
(IRQ_STATUS) first to clear the history.
Register 0x0F (IRQ_STATUS):
The IRQ_STATUS register contains the status of the pending interrupt requests.
Bit
7
6
5
4
3
2
1
0
+0x0F
Read/Write
Initial Value
BAT_LOW
R
0
TRX_UR
R
0
AMI
R
0
CCA_ED_DONE
R
0
TRX_END
R
0
RX_START
R
0
PLL_UNLOCK
R
0
PLL_LOCK
R
0
IRQ_STATUS
By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the issued
interrupt can be identified. A read access to this register resets all interrupt bits, and so clears
the IRQ_STATUS register.
If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be
read from IRQ_STATUS register even if the interrupt itself is masked. However in that case no
timing information for this interrupt is provided.
If register bit IRQ_MASK_MODE is set, it is recommended to read the interrupt status register
0x0F (IRQ_STATUS) first to clear the history.
30
8111C–MCU Wireless–09/09
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